This invention relates to a dynamic driving (or driver) circuit and, in particular, to a dynamic driving circuit for driving a signal line of an integrated circuit.
Traditionally, in a dynamic driving operation of a signal line in an integrated circuit, a high level at a dynamic node is achieved by holding electric charges. However, maintaining the high level by holding the electric charges makes the device susceptible to the influence of charge leakage or a noise. This possibly results in malfunction of the integrated circuit. In view of the above, use has been made of a dynamic driving circuit in order to improve data holding characteristics. For example, dynamic driving circuits of the type are disclosed in Japanese Unexamined Patent Publication (JP-A) No. 4-49407 (49407/1992) and "Principles of CMOS VLSI Design--A Systems Perspective--Second Edition" written by Neil H. E. Weste and Kamran Eshraghian, published in 1993, page 308, FIG. 5.36.
Two other dynamic driving circuits of the type will hereunder be described as first and second conventional dynamic driving circuits.
Referring to FIGS. 1 and 2, the first conventional dynamic driving circuit will be described.
As illustrated in FIG. 1, the first conventional dynamic driving circuit comprises first and second inverter circuits 1701 and 1702, first and second pMOS (p channel metal oxide semiconductor) transistors 1711 and 1712, and first and second nMOS (n channel metal oxide semiconductor) transistors 1721 and 1722. A clock signal (CLK) 1731 is inverted by the first inverter circuit 1701 to be supplied to gates of the first pMOS transistor 1711 and the first nMOS transistor 1721. A data signal (IN) 1732 is inverted by the second inverter circuit 1702 to be supplied to a gate of the second nMOS transistor 1722. A drain of the first pMOS transistor 1711 and a source of the second nMOS transistor 1722 are connected to a node N. A drain of the second nMOS transistor 1722 and a source of the first nMOS transistor 1721 are connected to each other. A drain of the first nMOS transistor 1721 is connected to ground. A drain and a gate of the second pMOS transistor 1712 are connected to the node N and ground, respectively.
The first conventional dynamic driving circuit of FIG. 1 is operable as shown in FIG. 2. In FIG. 2, a precharge period is a period in which the clock signal (CLK) 1731 has a high level. An evaluation (or sampling) period is another period in which the clock signal (CLK) 1731 has a low level.
When the clock signal (CLK) 1731 has a low level (that is, the driving circuit is put in the evaluation period) and the data signal (IN) 1732 has a high level, the first pMOS transistor 1711 and the second nMOS transistor 1722 are turned off. In this event, if the second pMOS transistor 1712 is not present, an output signal (OUT) 1741 would act as a dynamic node in a high-impedance (High-Z) state. By provision of the second pMOS transistor 1712 with its gate connected to ground, the output signal (OUT) 1741 is raised to a high level and maintains the high level, as illustrated in FIG. 2.
Referring to FIGS. 3 and 4, the second conventional dynamic driving circuit will be described.
As illustrated in FIG. 3, the second conventional dynamic driving circuit comprises first through third inverter circuits 1901, 1902, and 1903, first and second pMOS transistors 1911 and 1912, and first and second nMOS transistors 1921 and 1922. A clock signal (CLK) 1931 is inverted by the first inverter circuit 1901 to be supplied to gates of the first pMOS transistor 1911 and the first nMOS transistor 1921. A data signal (IN) 1932 is inverted by the second inverter circuit 1902 to be supplied to a gate of the second nMOS transistor 1922. A drain of the first pMOS transistor 1911 and a source of the second nMOS transistor 1922 are connected to a node N. A drain of the second nMOS transistor 1922 and a source of the first nMOS transistor 1921 are connected to each other. A drain of the first nMOS transistor 1921 is connected to ground. A drain of the second pMOS transistor 1912 is connected to the node N. An output signal (OUT) 1941 is inverted by the third inverter circuit 1903 into an inverted output signal (OUTB) 1942 to be supplied to a gate of the second pMOS transistor 1912.
In the second conventional dynamic driving circuit, the inverted output signal (OUTB) 1942 of the output signal (OUT) 1941 is connected to the gate of the second pMOS transistor 1912 so that, when the clock signal (CLK) 1931 has a low level (that is, the driving circuit is put in the evaluation period) and the data signal (IN) 1932 has a high level, the output signal (OUT) 1941 maintains a high level, as illustrated in FIG. 4.
Each of the above-mentioned first and the second dynamic driving circuits is provided with a charging arrangement (1712 or 1912) for supplying electric charges to a signal line even during the evaluation period (namely, when the clock signal (CLK) 1731 or 1931 has a low level). Thus, a charge level is maintained so as to enhance an immunity against noise and to reduce the possibility of malfunction.
Besides the first and the second conventional driving circuits mentioned above, proposal is made of several kinds of dynamic driving circuits which will presently be described.
Japanese Unexamined Patent Publication (JP-A) No. 63-195898 (195898/1988) discloses an integrated circuit comprising a signal line provided with a precharging arrangement and a positive feedback circuit operated during a discharge period of the signal line to amplify a signal to be transmitted to the signal line. In this integrated circuit, a discharge operation of the signal line to be discharged is promoted to thereby increase a signal transmission rate.
Japanese Unexamined Patent Publication (JP-A) No. 1-161913 (161913/1989) discloses a clock driving circuit comprising a first MOS switch inserted between a first potential and a clock signal output terminal and controllably turned on and off in response to an input clock signal, a second MOS switch inserted between a second potential and the clock signal output terminal and controllably turned on and off in response to the input clock signal, and a constant current supply circuit inserted between the first MOS switch and the first potential. In this clock driving circuit, it is possible to obtain an output clock signal having a constant rise rate and a constant fall rate.
Japanese Unexamined Patent Publication (JP-A) No. 1-175412 (175412/1989) discloses an integrated circuit comprising a plurality of logical operator blocks each of which is supplied with an input signal through an input signal line and executes a predetermined logical operation to produce a logical operation result as an output signal to be transmitted through an output signal line to an output side in response to a clock signal. Each logical operator block has a spare level setting unit for setting a level of at least one of the input and the output signal lines to a predetermined spare level. In this integrated circuit, it is possible to reduce a load capacitance so that an integration density is increased and to reduce a line resistance so that a response speed of a logical operator is increased.
Japanese Unexamined Patent Publication (JP-A) No. 2-124629 (124619/1990) discloses a bus driving circuit comprising three nMOSFETs and one pMOSFET. The bus driving circuit can perform a high-speed operation and is therefore applicable to a high-speed CMOS (complementary metal oxide semiconductor) integrated circuit.
However, the above-mentioned dynamic driving circuits have in the following disadvantages.
At first, a feedthrough current from a power supply to ground is caused to flow. When the feedthrough current flows, power consumption is increased and device deterioration due to EM (electro-migration) occurs. The feedthrough current is produced because, even during the transition to a low level, the signal line is supplied with electric charges through the charging arrangement so that a path from the power supply to ground (GND) is formed.
Second, a delay is increased. This is because, even during the transition to a low level, the signal line is supplied with electric charges through the charging arrangement so that the transition of the signal line is prevented.
Third, a circuit design is more complicated. This is because the charging arrangement must be inserted to the signal line at a required position.